Computer Organization & Architecture 2024 Q&A

Computer Organization & Architecture 2024 Q&A

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Q1.Convert the two decimal number X and Y to IEEE754 single precision arithmetic and then perform the floating point arithmetic to give the result Z in normalized floating point representation. Mention only 13 bits in the fraction part.  X=345.25 and Y=250.875 Z=X+Y

Answer: To perform floating-point arithmetic with IEEE754 single precision representation, let's first convert the given decimal numbers X and Y into their IEEE754 single precision binary representations. Then, we'll perform the addition and normalize the result.

Given: X=345.25X=345.25 and Y=250.875Y=250.875

1. Convert $345$ to binary: $345_{10}=101011001_2$
2. Convert $0.25$ to binary: $0.25_{10}=0.01_2$

So, $�$ in binary is $101011001.01$.

Now, let's normalize it: $1.0101100101\times 2^8$

In IEEE754, the exponent is represented using bias notation. The bias for single precision is $127$. So, the exponent $�$ for $�$ will be $8+127=135$ which in binary is $10000111$.

The fractional part (mantissa) is $01011001010000000000000$, but we only need 13 bits, so it becomes $0101100101000$.

Thus, $�$ in IEEE754 single precision format is:

$$\text{Sign bit: }0\text{Exponent: }10000111\text{Fraction: }0101100101000$$

For $�$:

1. Convert $250$ to binary: $250_{10}=11111010_2$
2. Convert $0.875$ to binary: $0.875_{10}=0.111_2$

So, $�$ in binary is $11111010.111$.

Now, let's normalize it: $1.1111010111\times 2^7$

The exponent $�$ for $�$ will be $7+127=134$, which in binary is $10000110$.

The fractional part (mantissa) is $11110101110000000000000$, but we only need 13 bits, so it becomes $1111010111000$.

Thus, $�$ in IEEE754 single precision format is:

$$\text{Sign bit: }0\text{Exponent: }10000110\text{Fraction: }1111010111000$$

Performing Floating Point Addition:

We'll add these two numbers in floating-point representation.

$$�=0100001110101100101000$$

$$�=0100001101111010111000$$

We need to align the exponents first. $�$ has a larger exponent, so we'll shift $�$'s mantissa to the right and decrease its exponent accordingly.

After aligning the exponents:

$$�=0100001110101100101000$$

$$�=0100001110111101011100$$

Now, we can simply add the mantissas:

$$\text{Sum}=0100001110101100101000+0100001110111101011100$$

Performing addition:

$$\text{Sum}=0100001111101000000100$$

Now, let's normalize this result. The exponent will be $135$, and the mantissa will be $1101000000100$.

Converting $�$ back to Decimal:

$�$ in binary is $1.1101000000100\times 2^{135}$.

Converting this back to decimal:

$�=(1+\frac{1}{2}+\frac{1}{4}+\frac{1}{8}+\frac{1}{64})\times 2^{135}$

$�=(1.8125)\times 2^{135}$

$�=(1.8125\times 2^{135}{)}_{10}$

This is the normalized form of the result $�$ in IEEE754 single precision arithmetic.

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Q2. Use Booth's algorithm to multiply two signed numbers, negative 9 and positive 2 to give the result (2X-9 = -18) where -9 is the  multiplier and 2 is the multiplicand.

Answer:  Booth's algorithm is used for signed binary multiplication. It reduces the number of additions required for multiplication by exploiting the sparsity of the multiplication by using a multiplier with fewer non-zero digits.

Here's how we can use Booth's algorithm to multiply -9 and 2:

Step 1: Convert numbers to binary:

-9: $9_{10}=1001_2$ (4-bit representation) 2: $2_{10}=0010_2$ (4-bit representation)

Step 2: Extend the numbers to the same number of bits (here, 5 bits):

-9: $1001_2$ (Original) 2: $00010_2$ (Padded with one zero on the left)

Step 3: Perform Booth's Algorithm Multiplication:

Initialize:

• Product = 00000
• Multiplier = 10010 (Negative 9 in Booth's algorithm)
• Multiplicand = 00010 (2)

Iteration 1:

• Last Bit = 0, Skip
• Second Last Bit = 1, Add Multiplicand (00010) to Product
  • Product = 00000 + 00010 = 00010
• Shift Right
  • Multiplier = 11001
  • Product = 00010

Iteration 2:

• Last Bit = 1, Subtract Multiplicand (00010) from Product
  • Product = 00010 - 00010 = 00000
• Second Last Bit = 0, Skip
• Shift Right
  • Multiplier = 11100
  • Product = 00000

Iteration 3:

• Last Bit = 0, Skip
• Second Last Bit = 0, Skip
• Shift Right
  • Multiplier = 11110
  • Product = 00000

Iteration 4:

• Last Bit = 0, Skip
• Second Last Bit = 0, Skip
• Shift Right
  • Multiplier = 11111
  • Product = 00000

Step 4: Interpret the Result:

The result of multiplying -9 and 2 using Booth's algorithm is 00000 in binary, which is 0 in decimal.

So, according to the provided information, the result $2�-9$ is not equal to -18. Therefore, there might be a mistake in the provided problem statement or the calculation.

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Q3. A zero address(stack) machine has the following instruction set for coding PUSH M, POP M, ADD,MUL,SUB,DIV

Write a program to obtain the following functionality X=(A+B)/(C-D*E*F)

Answer: Here is a program that implements the desired functionality X=(A+B)/(C-DEF) using a zero address stack machine:

; Initialize stack

MOV SP, #0x1000

; Load values into registers

MOV R0, #0x3f80 ; A = 1.0

MOV R1, #0x4000 ; B = 2.0

MOV R2, #0x4040 ; C = 3.0

MOV R3, #0x4000 ; D = 2.0

MOV R4, #0x3f80 ; E = 1.0

MOV R5, #0x3f80 ; F = 1.0

; Perform calculations

PUSH R0 ; PUSH A

PUSH R1 ; PUSH B

ADD R6, R0, R1 ; R6 = A + B

PUSH R6 ; PUSH R6

MUL R7, R3, R4 ; R7 = D * E

MUL R8, R7, R5 ; R8 = D * E * F

SUB R9, R2, R8 ; R9 = C - D * E * F

PUSH R9 ; PUSH R9

DIV R10, R6, R9 ; R10 = (A + B) / (C - D * E * F)

; Store result in memory

MOV [0x2000], R10

; Halt program

HLT

This program initializes the stack pointer (SP) to 0x1000. It then loads the values A, B, C, D, E, and F into registers R0-R5. The program performs the calculations X=(A+B)/(C-DEF) using the ADD, MUL, and SUB instructions. The result is stored in memory at address 0x2000. Finally, the program halts.

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Q4. When comparing two computer C1 and C2, C1 has the machine instructions for the FP operations, while C2 has not . The clock frequency on both computers is 200 MHz. In both cases, we run the same programme, which includes the following commands.

 

Type the command         Dynamic Share of                             Instruction duration (CPLi)

                                                Instructions in program(pi)             C1                        C2

FP addition                                         18%                                          8                         18

FP Multiplication                              12%                                            10                        34          

FP Division                                          6%                                           6                         62

Non- FP instruction                         64%                                             3                            3

a) Calculate the MIPS for C1 and C2.

b) Calculate the CPU program execution time on the computers C1 and C2, if there are 14000 instructions in the program?

c) Find the ratio of average CPI if two independent improvements are made in C2, if in 1st case FP multiplication is improved so that it takes only 10 cycles and others all remaining the same or in the 2nd case FP division instruction is improved and it takes only 12 cycles.

Answer: 

a)

a) Calculate the MIPS for C1 and C2:

MIPS (Million Instructions Per Second) is calculated using the formula:

$$\text{MIPS}=\frac{\text{Clock frequency (Hz)}}{\text{CPI}\times 10^6}$$

Where CPI is the Average Cycle Per Instruction.

For C1:

• ${\text{CPI}}_{\text{C1}}=(0.18\times 8)+(0.12\times 10)+(0.06\times 6)+(0.64\times 3)=1.44$
• ${\text{MIPS}}_{\text{C1}}=\frac{200\times 10^6}{1.44\times 10^6}=\frac{200}{1.44}\approx 138.89\text{ MIPS}$

For C2:

• ${\text{CPI}}_{\text{C2}}=(0.18\times 18)+(0.12\times 34)+(0.06\times 62)+(0.64\times 3)=10.68$
• ${\text{MIPS}}_{\text{C2}}=\frac{200\times 10^6}{10.68\times 10^6}=\frac{200}{10.68}\approx 18.73\text{ MIPS}$

b) Calculate the CPU program execution time on the computers C1 and C2:

The CPU program execution time (in seconds) is calculated using the formula:

$$\text{Execution time}=\frac{\text{Number of instructions}\times \text{CPI}}{\text{Clock frequency}}$$

For C1:

• ${\text{Execution time}}_{\text{C1}}=\frac{14000\times 1.44}{200\times 10^6}$

For C2:

• ${\text{Execution time}}_{\text{C2}}=\frac{14000\times 10.68}{200\times 10^6}$

To solve this problem, let's break it down into steps:

a) Calculate the MIPS for C1 and C2:

MIPS (Million Instructions Per Second) is calculated using the formula:

$$\text{MIPS}=\frac{\text{Clock frequency (Hz)}}{\text{CPI}\times 10^6}$$

Where CPI is the Average Cycle Per Instruction.

For C1:

• ${\text{CPI}}_{\text{C1}}=(0.18\times 8)+(0.12\times 10)+(0.06\times 6)+(0.64\times 3)=1.44$
• ${\text{MIPS}}_{\text{C1}}=\frac{200\times 10^6}{1.44\times 10^6}=\frac{200}{1.44}\approx 138.89\text{ MIPS}$

For C2:

• ${\text{CPI}}_{\text{C2}}=(0.18\times 18)+(0.12\times 34)+(0.06\times 62)+(0.64\times 3)=10.68$
• ${\text{MIPS}}_{\text{C2}}=\frac{200\times 10^6}{10.68\times 10^6}=\frac{200}{10.68}\approx 18.73\text{ MIPS}$

b) Calculate the CPU program execution time on the computers C1 and C2:

The CPU program execution time (in seconds) is calculated using the formula:

$$\text{Execution time}=\frac{\text{Number of instructions}\times \text{CPI}}{\text{Clock frequency}}$$

For C1:

• ${\text{Execution time}}_{\text{C1}}=\frac{14000\times 1.44}{200\times 10^6}$

For C2:

• ${\text{Execution time}}_{\text{C2}}=\frac{14000\times 10.68}{200\times 10^6}$

c) Find the ratio of average CPI if two independent improvements are made in C2:

Improvement 1: FP multiplication improved to 10 cycles

• New ${\text{CPI}}_{\text{C2\_improved1}}=(0.18\times 18)+(0.12\times 10)+(0.06\times 62)+(0.64\times 3)=7.12$

Improvement 2: FP division improved to 12 cycles

• New ${\text{CPI}}_{\text{C2\_improved2}}=(0.18\times 18)+(0.12\times 34)+(0.06\times 12)+(0.64\times 3)=8.52$

Ratio of average CPI:

• For improvement 1: $\frac{10.68}{7.12}$
• For improvement 2: $\frac{10.68}{8.52}$

Let's calculate these values.

Calculation:

a)

• ${\text{MIPS}}_{\text{C1}}=138.89\text{ MIPS}$
• ${\text{MIPS}}_{\text{C2}}=18.73\text{ MIPS}$

b)

• ${\text{Execution time}}_{\text{C1}}=\frac{14000\times 1.44}{200\times 10^6}$ seconds
• ${\text{Execution time}}_{\text{C2}}=\frac{14000\times 10.68}{200\times 10^6}$ seconds

c)

• Improvement 1: $\frac{10.68}{7.12}$
• Improvement 2: $\frac{10.68}{8.52}$

Now, let's calculate these values.

Calculation:

a)

• ${\text{MIPS}}_{\text{C1}}=138.89\text{ MIPS}$
• ${\text{MIPS}}_{\text{C2}}=18.73\text{ MIPS}$

b)

• ${\text{Execution time}}_{\text{C1}}=\frac{14000\times 1.44}{200\times 10^6}$ seconds
• ${\text{Execution time}}_{\text{C2}}=\frac{14000\times 10.68}{200\times 10^6}$ seconds

c)

• Improvement 1: $\frac{10.68}{7.12}\approx 1.498$
• Improvement 2: $\frac{10.68}{8.52}\approx 1.253$

Results:

a)

• ${\text{MIPS}}_{\text{C1}}\approx 138.89\text{ MIPS}$
• ${\text{MIPS}}_{\text{C2}}\approx 18.73\text{ MIPS}$

b)

• ${\text{Execution time}}_{\text{C1}}\approx 0.1008$ seconds
• ${\text{Execution time}}_{\text{C2}}\approx 0.7494$ seconds

c)

• Improvement 1: $\frac{10.68}{7.12}\approx 1.498$
• Improvement 2: $\frac{10.68}{8.52}\approx 1.253$

These are the calculated values based on the given instructions and data.

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Q5. (A) a. Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock 3124-2022 frequency supplied to the microprocessor? Explain to substantiate the approach.

Answer: 

Given:

• Bus cycle duration = 4 input clock cycles.
• External data bus width = 16 bits.
• Input clock frequency = 8 MHz.

Maximum Data Transfer Rate (Mbps):

First, let's calculate the maximum data transfer rate (in bits per second) that the microprocessor can sustain across the bus:

$$\text{Maximum Data Transfer Rate (bits/s)}=\frac{\text{External data bus width}}{\text{Bus cycle duration}}$$

Substituting the given values:

$$\text{Maximum Data Transfer Rate (bits/s)}=\frac{16\text{ bits}}{4\text{ cycles}}=4\text{ bits/cycle}$$

Convert to bytes per second:

To convert from bits per cycle to bytes per second, we need to consider the clock frequency. Since each cycle transfers 16 bits, and there are $8\times 10^6$ cycles per second (8 MHz), we can calculate the transfer rate in bytes per second as follows:

$$\text{Maximum Data Transfer Rate (bytes/s)}=\frac{\text{Maximum Data Transfer Rate (bits/s)}}{8}\times \text{Clock frequency (Hz)}$$

Substituting the given values:

$$\text{Maximum Data Transfer Rate (bytes/s)}=\frac{4\text{ bits/cycle}}{8}\times 8\times 10^6\text{ cycles/s}$$

$$=0.5\times 10^6\text{ bytes/s}$$

$$=500,000\text{ bytes/s}$$

Increasing Performance:

To increase the performance, we have two options: increase the external data bus width or double the external clock frequency.

1. Increase external data bus width to 32 bits:

   • If we increase the external data bus width to 32 bits, the maximum data transfer rate will double, as each cycle will transfer 32 bits instead of 16 bits. Therefore, the new maximum data transfer rate would be $2\times 500,000\text{ bytes/s}=1,000,000\text{ bytes/s}$.

2. Double the external clock frequency:

   • If we double the external clock frequency to 16 MHz, the maximum data transfer rate will also double. Therefore, the new maximum data transfer rate would be $2\times 500,000\text{ bytes/s}=1,000,000\text{ bytes/s}$.

Both increasing the external data bus width to 32 bits and doubling the external clock frequency would result in the same maximum data transfer rate of $1,000,000\text{ bytes/s}$. However, doubling the external clock frequency might have additional implications such as increased power consumption and heat generation, while increasing the data bus width could potentially require changes in the microprocessor's architecture and external hardware. Therefore, the choice between the two options would depend on various factors including power constraints, design complexity, and compatibility with existing systems.

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Q5 (B). Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16- bit microprocessor. Assume that, on average, 30% of the operands and instructions are 32 bits long, 40% are 16 bits long, and 30% are only 8 bits long. Calculate the improvement achieved in the number of bus cycles when fetching instructions and 12 operands with the 32-bit microprocessor to a 16 bit microprocessor. When the number of instructions is 100.

Answer: 

To calculate the improvement achieved in the number of bus cycles when fetching instructions and operands with the 32-bit microprocessor compared to a 16-bit microprocessor, we need to consider the average operand and instruction lengths and the number of instructions.

Given:

• Average operand and instruction lengths:
  • 30% are 32 bits long.
  • 40% are 16 bits long.
  • 30% are 8 bits long.
• Number of instructions = 100.

Let's first calculate the number of cycles required for both microprocessors to fetch instructions and operands.

For the 16-bit microprocessor:

• 30% of the time, it will need 2 bus cycles to fetch a 32-bit operand or instruction (16 bits at a time).
• 40% of the time, it will need 1 bus cycle to fetch a 16-bit operand or instruction.
• 30% of the time, it will need 1 bus cycle to fetch an 8-bit operand or instruction.

For the 32-bit microprocessor:

• 30% of the time, it will need 1 bus cycle to fetch a 32-bit operand or instruction.
• 40% of the time, it will need 1 bus cycle to fetch a 16-bit operand or instruction.
• 30% of the time, it will need 1 bus cycle to fetch an 8-bit operand or instruction.

Let's calculate the total number of bus cycles for both microprocessors.

For the 16-bit microprocessor:

$$\text{Total bus cycles}=(30\mathrm{\%}\times 2\text{ cycles}\times 100)+(40\mathrm{\%}\times 1\text{ cycle}\times 100)+(30\mathrm{\%}\times 1\text{ cycle}\times 100)$$

$$=(60+40+30)\text{ cycles}$$

$$=130\text{ cycles}$$

For the 32-bit microprocessor:

$$\text{Total bus cycles}=(30\mathrm{\%}\times 1\text{ cycle}\times 100)+(40\mathrm{\%}\times 1\text{ cycle}\times 100)+(30\mathrm{\%}\times 1\text{ cycle}\times 100)$$

$$=(30+40+30)\text{ cycles}$$

$$=100\text{ cycles}$$

Now, let's calculate the improvement achieved in the number of bus cycles by using the 32-bit microprocessor compared to the 16-bit microprocessor.

$$\text{Improvement}=\frac{\text{Total bus cycles for 16-bit microprocessor}-\text{Total bus cycles for 32-bit microprocessor}}{\text{Total bus cycles for 16-bit microprocessor}}\times 100\mathrm{\%}$$

$$=\frac{130-100}{130}\times 100\mathrm{\%}$$

$$=\frac{30}{130}\times 100\mathrm{\%}$$

$$\approx 23.08\mathrm{\%}$$

Therefore, the improvement achieved in the number of bus cycles when fetching instructions and operands with the 32-bit microprocessor compared to the 16-bit microprocessor is approximately $23.08\mathrm{\%}$.

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