Synopsys Hiring Fresher Software Application Engineer 2024 | Bachelor’s or Master’s degree

Synopsys re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

Synopsys  seeking a highly motivated  Software Application Engineer  with expertise in hierarchical flow knowledge and experience in various top-level implementation flows.

Synopsys Hiring Fresher Software Application Engineer 2024

Job Designation : Software Application Engineer

Qualification : Bachelor’s or Master’s degree

Experience : Freshers

Location : Hyderabad, Telangana, India


Synopsys Hiring Fresher Software Application Engineer





Job Description :

Applications Engineer position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an fresher and motivated individual who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved.
  1. Develop and implement hierarchical flow methodologies for complex ASIC designs.
  2. Work closely with cross-functional teams including architects, RTL designers, physical designers and verification teams to ensure high quality and timely delivery of design products.
  3. Analyze timing reports and work with design teams to resolve timing issues.
  4. Optimize design for power, performance and area.
  5. Perform floor planning and place-and-route of top-level modules.
  6. Participate in the development of new design methodologies and flows to improve design quality, efficiency and time-to-market.
Location : Hyderabad, Telangana, India


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Skill Set :

  1. Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog
  2. Strong understanding of hierarchical design methodologies.
  3. Good working knowledge on UNIX, Tcl and/or any other scripting language to be effective
  4. Exposure to dynamic simulation verification covering System Verilog, Verilog, methodologies, debug, low power, coverage is an advantage
  5. Exposure to Synopsys EDA tools (VCS, Verdi) would be an added advantage
  6. Team player, partners with multiple stakeholders, has attention to detail and innovative mindset
  7. Motivated, doer and self-organized team worker with good social communication skills
  8. Open to travel, ability to multi-task, be detail-oriented
  9. Excellent written and oral communication skills is a must as the role requires interfacing with clients, review their challenges, proposing solutions


How to Apply

All interested and eligible candidates can apply online by the following link as soon as possible.

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